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December 1998 PRELIMINARY
ML6430/ML6431* Genlocking Sync Generator with Digital Audio Clock for NTSC, PAL & VGA
GENERAL DESCRIPTION
The ML6430/ML6431 are multi-standard single-chip BiCMOS video Genlock ICs for NTSC, PAL and VGA. They are designed to provide a stable clock from an analog video signal, and to provide timing pulses for clamping, decoding, blanking and processing video signals. The ML6430/ML6431 handle VCR glitches and variations created by head switching, tape dropouts, missing sync pulses, freeze frames, high speed playback and camcorder gyro errors. The ML6430/ML6431 are designed for high noise immunity, insensitivity to varying signal amplitudes, overmodulated color carriers, and sync glitches. Advanced analog and digital clock synthesis techniques provide multi-standard and non-standard operation from a single crystal or external asynchronous clock source. Pin selectable preset modes allow operation for most video standards in simple stand-alone mode without the necessity of using the serial bus. For more demanding applications, a two wire serial control bus is available for full control of all of the ML6430/ML6431 features. The ML6430/ML6431 are ideal for clock generation in MPEG encoders, high performance display timing, and video editing.
FEATURES
s s s s s s s s s s s s
Line locked scalable horizontal pixel clock for an arbitrary number of pixels per line Standard frequencies of 12.27, 13.5, 14.75MHz, or 4Fsc 4/2 or 2/1 clock outputs (54 and 27MHz, or 27 and 13.5MHz) and VGA clocks Audio clocks: 32, 44.1, or 48kHz, locked to video On-chip sync separator, VCO and pulse generator Low clock jitter: Short Term: <200ps rms locked Line to line: <600ps rms (2.2ns peak-to-peak) locked Fast recovery from VCR head switch, stable for fast shuttle speeds and pause Single crystal or external frequency source PAL, NTSC or VGA operation 2 wire serial control bus, or selectable presets for stand alone operation RS170A compatible
* This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
4 9 21 29
CVIN/ HSYNC
6
VCC S
VCC A
VCC B MUX
VCC D CSYNC
26
SYNC SEPARATOR
7
CVREF NOSIGNAL SIGNAL DETECT VSYNC
14
8
ANALOG PLL XTALIN CRYSTAL OSC. XTALOUT
12
DIGITAL PLL DIGITAL PHASE DET. AND FILTERING REF VCO DIGITAL PHASE MOD. HORIZ. PIXEL COUNTER VERT. LINE COUNTER DYNA. STATE MACH. CONTROLLER
LOCKED HRESET FRESET SCLAMP BCLAMP/BURST 1X CLOCK/4X CLOCK 2X CLOCK HBLANK VBLANK
15 23 22 28 27 19 18
11
/M
PHASE DETECTOR
/N
31 32 1 2
P0 P1 P2/S DATA P3/S CLK SLEEP/54MHz
3
25 24 17 16
SERIAL CONTROL AND PRESETS FREERUN
13
PULSE AND AUDIO CLOCK GENERATOR GND S
5
FIELD ID AUDIOCLK/PHERROUT* GND D
*PHERROUT IS ONLY AVAILABLE IN ML6431 30
GND A
10
GND B
20
1
ML6430/ML6431
PIN CONFIGURATION
ML6430 32-Pin TQFP (H32-7)
BCLAMP/BURST
P2/SDATA P3/SCLK SLEEP/54MHz VCC S GND S CVIN/HSYNC CVREF VSYNC
32 31 30 29 28 27 26 25 24 1 2 3 4 5 6 7 8 9 23 22 21 20 19 18 17 10 11 12 13 14 15 16
HBLANK
SCLAMP
GND D
CSYNC
VCC D
P1
P0
VBLANK HRESET FRESET VCC B GND B 1X CLOCK/4X CLOCK 2X CLOCK FIELD ID
XTALOUT
FREERUN
NOSIGNAL
LOCKED CSYNC
XTALIN
TOP VIEW
ML6431 32-Pin TQFP (H32-7)
BCLAMP/BURST
P2/SDATA P3/SCLK SLEEP/54MHz VCC S GND S CVIN/HSYNC CVREF VSYNC
32 31 30 29 28 27 26 25 24 1 2 3 4 5 6 7 8 9 23 22 21 20 19 18 17 10 11 12 13 14 15 16
HBLANK
SCLAMP
GND D
VCC D
P1
P0
AUDIOCLK
GND A
VCC A
VBLANK HRESET FRESET VCC B GND B 1X CLOCK/4X CLOCK 2X CLOCK FIELD ID
XTALOUT
TOP VIEW
2
AUDIOCLK/PHERROUT
GND A
XTALIN
FREERUN
NOSIGNAL
LOCKED
VCC A
ML6430/ML6431
PIN DESCRIPTION
PIN NAME
(NOTE: ML6430 and ML6431 pin functions are identical except for pin 16. See below)
PIN NAME FUNCTION
FUNCTION
1
P2/SDATA
This is a dual function pin. If presets are enabled, refer to Table 7. If presets are disabled, serial bus data input. This is a dual function pin. If presets are enabled, refer to Table 7. If presets are disabled, serial bus clock input.
13
FREERUN
2
P3/SCLK
Forces the PLL to run at a selected standard without syncing to a video signal. Accuracy is 20ppm in FREERUN with ideal crystal, otherwise locked to video source
14
3
SLEEP/54MHz Hardware sleep mode: when low, disables entire chip for ultra-low power dissipation. Sleep mode can also be enabled/disabled via serial bus (Register 8). 54MHz is a clock input. This can be any 4X clock up to 70MHz used for pulse generation. 15 VCC S GND S Analog supply for sync separator. Analog ground for sync separator. 16
NOSIGNAL Indicates video signal activity has not been detected at the composite input. If NOSIGNAL = low, this condition does not imply that lock has been established. The NOSIGNAL pin can be tied to FREERUN to create a local loop in which the genlock will not try to lock until a signal is detected at the input. LOCKED Indicates when digital PLL is locked to incoming video signal.
4 5 6
CVIN/HSYNC Composite video input; video input in typical composite video applications, or Y input for YUV applications, or G input for RGB applications with sync on green. For typical VGA or other high performance display applications, this input may be supplied with a TTL level HSYNC signal and the vertical sync input supplied with a TTL level VSYNC signal. CV REF Reference voltage for internal sync slicer. The external capacitor is driven by a charge pump to follow the sync tip. Vertical input for non-composite sources. This input may be supplied with a TTL level VSYNC signal. For composite inputs this pin is tied high or low. Analog supply pin for analog PLL. Analog ground for analog PLL. Crystal may be parallel tuned 3.58 MHz or 4.43MHz, or may be driven by an external oscillator at these frequencies, or at 4x these frequencies. Crystal drive pin. No connect if using external oscillator or clock.
(ML6430) AUDIOCLK Digital audio clock output. Programmable for 32kHz, 44.1kHz or 48kHz output. (ML6431) AUDIOCLK/PHERROUT This is a dual mode pin. Pin is selected via serial bus (Register 7). AUDIOCLK is an audio clock signal (see Table 9). PHERROUT indicates whether incoming HSYNC is ahead or behind output HSYNC. FIELD ID Field Flag: Odd = 1, Even = 0
16
7
17 18
2X CLOCK 2X oversampled PIXEL CLOCK & Output of Digital PLL. Nominal frequency of 27MHz 1X CLOCK/4X CLOCK 1X pixel clock. Nominal frequency of 13.5MHz or 54MHz 20ppm in FREERUN with ideal crystal, otherwise locked to video source. PAL 4X CLOCK not available (no 4x4.4336MHz clock). GND B VCC B F RESET Digital ground for output driver buffers. Digital supply for output driver buffers. Frame reset; active low for one half line at the high to low transition of field ID. In NTSC mode, FRESET goes low on the high-to-low transition on the Field ID pin and at the beginning of line 1 (see Figure 2). In PAL mode, FRESET goes low on the high-to-low transition on the Field ID pin and at the end of line 310 (see Figure 3).
8
V SYNC
19
9 10 11
VCC A GND A XTALIN
20 21 22
12
XTALOUT
3
ML6430/ML6431
PIN DESCRIPTION
PIN NAME
(Continued) PIN 28 NAME SCLAMP FUNCTION Sync clamp pulse occurs just after leading edge of sync. Duration is typically less than 50% of sync pulse to avoid problems with equalizers in the vertical interval, active high. Digital supply pin for digital PLL. Digital ground pin for digital PLL. This is a three-state pin: low means serial bus is enabled, high or unconnected (high Z) means presets are active. Refer to Table 7. This is a three state pin. Refer to Table 7. If presets are disabled pin is ignored.
FUNCTION
23 24 25 26
H RESET V BLANK H BLANK C SYNC
Horizontal reset; active low for one half pixel. Vertical blanking, active low Horizontal blanking, active low
29 Composite sync output. May be either the raw output of sync slicer, or regenerated signal from internal pulse generators. If raw slicer output is selected, then signals disappear when input signal disappears. If regenerated output is selected, then signal is always present regardless of input conditions. Preset modes produce regenerated sync. 30 31
VCC D GND D P0
32
P1
27
BCLAMP/BURST This is a dual mode pin. User may select either a back porch clamp pulse or a burst gate pulse via the serial control bus. Preset is BCLAMP pulse.
4
ML6430/ML6431
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. DC Supply Voltage (VCC A & VCC D) ............. -0.3V to 7V Analog & Digital Inputs/Outputs ... -0.3V to VCC A + 0.3V Input current per pin ............................................. 25mA Storage Temperature ............................... - 65C to 150C Junction Temperature .............................................. 125C
OPERATING CONDITIONS
Supply Range ............................................... 4.5V to 5.5V Temperature Range ....................................... 0C to 70C Thermal Resistance ............................................. 80C/W
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 4.5 to 5.5V and TA = 0 to 70C, CIN = 0.1F, CREF = 0.1F (Note 1).
PARAMETER SUPPLY Supply Current (Analog and Digital) Analog Supply Current Digital Supply Current DIGITAL INPUTS Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Input Capacitance TTL INPUTS (HSYNC, VSYNC) VIL V IH Input Low Voltage Input High Voltage 2.0 0.8 V V VIN = 0V + 0.1V VIN = VCC D - 0.1V 2 0 VCC - 0.8 0.8 V CC 1.0 1.0 V V A A pF VCC A = VCC D = 4.5 Max programmed clock rates 80 35 45 120 mA mA mA CONDITIONS MIN TYP MAX UNITS
THREE STATE DIGITAL INPUTS Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Input Capacitance Mid Level Input Voltage with 5V Supply DIGITAL OUTPUTS Low Level Output Voltage High Level Output Voltage CLOAD : Output Capacitance Output Disable Leakage 0 VCC - 0.5 50 10 0.5 V V pF A 2 VIN = 0V VIN = VCC D 0 VCC - 0.8 50 50 2 3 150 150 0.8 V V A A pF V
5
ML6430/ML6431
GENLOCK PERFORMANCE SPECIFICATIONS
Unless otherwise noted, VIN = 1 VPP NTSC test signal for composite inputs, or 100% color bars for component (Note 1). See Figure 1 for parameter measurement definition
PARAMETER SYNC SEPARATION Min Sync Amplitude Max Video Amplitude Clamp timing error Clamp Recovery TIme CLOCK RECOVERY Short Term Output Jitter Rejection RMS Residual Output Clock Jitter Peak to Peak (6s), Line to Line Jitter Head Switch Recovery Time to 1ns Error Step Frequency Recovery Time to 1ns Error Missing Sync Sensitivity Sync Glitch Sensitivity 4X Clock Duty Cycle 2X Clock Duty Cycle 1X Clock Duty Cycle Clock Skew -- 1X to 2X Pulse Output Rise Time Pulse Output Fall Time Pulse Output Setup Time Pulse Output Hold Time Input jitter = 50ns RMS Input jitter <1ns RMS Input Jitter < 1ns 5s step H change on or before line 1 1% step H frequency change on or before line 1 (Note 4) (Note 5) CLOAD = 50pF, fCLK4X < 60MHz CLOAD = 50pF, fCLK2X < 30MHz CLOAD = 50pF, fCLK1X < 15MHz CLOAD = 50pF, fCLK1X < 15MHz CLOAD = 50pF CLOAD = 50pF CLOAD = 50pF CLOAD = 50pF 2 2 20 20 40 48 48 -15 600 2.0 4 12 1.0 1.0 60 52 52 6 10 10 15 2.2 dB ps ns lines ms ns ns % % % ns ns ns ns ns NTC7 AC bounce signal (Note 2) NTC7 DC bounce signal (Note 3) 135 3 10 16 mV V ns s CONDITIONS MIN TYP MAX UNITS
SERIAL BUS
PARAMETER INPUT Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Input Impedance fCLK = 100kHz Input Capacitance (CIN) SYSTEM TIMING SCLK Frequency (fCLOCK) Input Hysteresis (VHYS) Spike Suppression (tSPIKE) Power Setup Time to Valid Data Inputs Max length for zero response VCC Settled to Within 1% 10 0.2 50 100 kHz V ns ms VIN = 0V VIN = VCC D 1 2 0 VCC - 0.8 0.8 V CC 1.0 1.0 V V mA mA MW pF CONDITIONS MIN TYP MAX UNITS
6
ML6430/ML6431
SERIAL BUS LOGIC
PARAMETER SYSTEM TIMING (Continued) Wait Time From STOP to START On SDATA (tWAIT) Hold Time for START On SDATA (tHD/START) Setup Time for START On SDATA (tSU/START) Min LOW Time On SCLK (tLOW) Min HIGH Time On SCLK (tHI) Hold Time On SDATA (tHD/DATA) Setup Time On (tSU/DATA) Fast mode (Note 2) Slow mode (Note 2) Rise Time for SCLK & SDATA (tLH) Fall Time for SCLK & SDATA (tHL) Setup Time for STOP On SDATA (tSU/STOP)
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: Parameter is Luma dependent. Note 3: Reclock time after bounce. Note 4: Net phase error for single isolated missing H pulse. Note 5: Net phase error for glitch at sync level <50ns.
(Continued)
CONDITIONS MIN TYP MAX UNITS
1.3 0.6 0.6 1.3 0.6 5.0 100 250 30 30 0.6 300 300
s s s s s s ns ns ns ns s
COMPOSITE VIDEO IN PIN 6 REGENERATED CSYNC PIN 26 EQUALIZERS tHSW tHEQW
SERRATIONS tHBLK tHBLKW tHSTC SCLAMP PIN 28
tHSERRW
HBLANK PIN 25
tHSTCW BGATE PIN 27 tHBPC BCLAMP PIN 27 tHBPCW HRESET PIN 23 tHRW tHBPGW
NOTE: NOT TO SCALE
Figure 1. Line Rate Waveforms
7
ML6430/ML6431
DEVICE DIFFERENCES
Tables 1 and 2 summarize the differences between the ML6430 and ML6431. The pinouts of the ML6430 and the ML6431 are the same with the exception that the ML6431 has a few enhancements, (Center Frequency and Free Run Mode, see Table 1) and added functionality (see Table 2).
DEVICE Video Formats, Timing, and Pulse Generation
NTSC PAL
FUNCTIONAL DESCRIPTION Clock Rates
CCIR601 Square Pixel 4xFSC
Input Crystal
3.58 MHz 4.43 MHz
Free Run Mode
VGA Clock
VCR Lock
ML6430
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ML6431
Yes
Yes*
Yes
Yes*
Yes
Yes
Yes
Yes. Limited transition between free run modes 1 and 2. (Figure 4) Yes. Faster transition between freerun modes 1and 2. (Figure 4a)
Yes. Limited to 640x480 pixel clock.
Yes
Yes. Works up to 75MHz. (Table 6)
Yes.
* Readjusted the center frequency for PAL square pixel with NTSC crystal to achieve greater than +/-5% range. See Table 4
Table 1. Summary of Functional Differences between the ML6430 and ML6431.
DEVICE
MODE
REGISTER DIFFERENCES Register 7, Bit 2 0 1 0 1 X
PIN OUT DIFFERENCES
ML6430
ML6431
Sleep Mode Pulse Generator Mode* Time Base Correction Mode Sleep Mode Pulse Generator Mode* PHERROUT Mode*
Register 7, Pin 3 Pin 16 Bit 3 0 SLEEP AUDIOCLK 0 54MHz** AUDIOCLK This function not available in the ML6430 0 SLEEP AUDIOCLK 0 54MHz** AUDIOCLK 1 Must be set HIGH PHERROUT
*For these modes the SLEEP mode can only be enable/disabled via serial bus (Register 8). **The 54MHz clock input (pin 3) can be any 4 x Clock up to 70MHz
Table 2. Summary of Register Differences between the ML6430 and ML6431.
8
ML6430/ML6431
FUNCTIONAL DESCRIPTION
DUAL PLLS The Genlock has the following properties: * A stable, asynchronous crystal controlled oscillator provides the basic timing signals. * A precision analog circuit uses the above timing signals to generate an arbitrarily phased output whose phase can be altered at pixel rate. * A digital PLL loop monitors the error signal from a digital phase detector, and generates a pixel by pixel phase adjustment of the output. * An intelligent state machine further enhances performance by monitoring errors and error history and adjusting the gains of the loop accordingly. * A circuit automatically detects a VCR signal and increases loop gain for proper tracking and minimum jitter. The digital PLL has five operating modes. In normal operation with a stable input the controller will settle to state 1. If errors are large and consistent, controller will move to state 5. If error conditions are corrected, controller will sequentially decrease the state as the errors are reduced toward 0. If small but consistent errors persist while controller is in state 1, then controller may move to states 2 or 3 to help settle out errors more quickly. None of these changes will cause a reset of pixel count, or a discontinuity of output clocks. Operating modes are described in greater detail below. 1. Normal: Gain is low, instantaneous phase gain is 1/32, giving a net short term jitter gain (output/input jitter) of about -30db. Full peak to peak jitter (including lower frequency jitter) from a white source is about 15db. 2. Slow: Gain is increased by 4x, and settling time reduced by about the same. This mode is used as a transition mode during normal lock sequence, or as a modest speed up mode if errors are high. 3. Medium: Gain is increased by 8x, and settling time reduced by about the same. This mode is used as a transition mode during normal lock sequence, or as a speed up mode if errors are consistently high. 4. Fast: Gain is increased by 16x. Adds frequency adjustments to mode 5 for fast settling during hot switches or pathological gyro errors in hand held camcorders. 5. Phase: Only Gain is 16x for phase changes, 0 for frequency changes. Primarily used to quickly settle head switch phase errors without affecting loop frequency. LOW POWER SLEEP MODES Sleep mode may be initiated either from the serial control bus, or from an external pin. In both cases the entire chip except the serial bus is shut down. For applications where PHERROUT is used, the sleep mode can only be enabled/ disabled via serial control. PHERROUT SIGNAL The PHERROUT pin indicates, on a line by line basis, whether the H SYNC pulse of the analog input signal is leading or trailing the genlock's output H SYNC pulse. This information is used by the genlock to decide whether to speed up or slow down the internal clock to achieve locking of the H SYNC pulses. If PHERROUT = 0, then the analog sync is ahead; therefore, the internal clock will speed up in an effort to lock the H SYNC pulses. By contrast, if PHERROUT = 1, then the analog sync is behind; therefore, the internal clock will slow down in an effort to lock the H SYNC pulses. Ultimately, when the genlock is locked to the incoming analog signal, PHERROUT will alternate approximately every line between 0 and 1. PHERROUT (PIN 16) 0 1 DESCRIPTION Speed up output timing Slow down output timing
Table 3. PHERROUT Signal Description SYNC SEPARATION Sync separation is accomplished using peak tracking analog amplifiers with a precision sync slicer. The closed tracking loop is equipped with timers to discriminate true sync pulses from noise glitches or chroma overshoots. The use of analog sync separation techniques removes a serious source of jitter present in most digital PLLs. CRYSTAL SELECTION The precision crystal source for the ML6430/ML6431 can be supplied in one of four ways. An industry standard 3.58MHz parallel tuned NTSC color subcarrier crystal or a 4.43MHz parallel tuned PAL color subcarrier crystal may be used. Alternately, a 14.318MHz NTSC or 17.7MHz PAL, 4xFs, or a 3.58MHz or 4.43MHz oscillator source may be used. Regardless of the crystal used, the ML6430/ ML6431 can lock to PAL, NTSC, Beta or MII or YUV in either 625 or 525 standards. Table 4 provides the clock rate accuracy for both the NTSC and PAL clock rates for each crystal selected. Note that the range may vary between the ML6430 and the ML6431.
9
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued)
CENTER FREQUENCY AND RANGE FOR EACH FREQUENCY STANDARD OF THE ML6431 VIDEO STANDARD CLOCK RATE CLOCK RATE ACCURACY CENTER FREQUENCY AND RANGE FOR EACH FREQUENCY STANDARD OF THE ML6430 VIDEO STANDARD CLOCK RATE CLOCK RATE ACCURACY
3.58MHz Crystal NTSC Square Pixel NTSC 601 NTSC 4fsc PAL Square Pixel PAL 601 PAL 4fsc 4.43MHz Crystal NTSC Square Pixel NTSC 601 NTSC 4fsc PAL Square Pixel PAL 601 PAL 4fsc
4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk=
49.09MHz 54.00MHz 57.27MHz 59.00MHz 54.00MHz 35.47MHz 49.09MHz 54.00MHz 57.27MHz 59.00MHz 54.00MHz 35.47MHz
+8.35%/ -5.19% +6.07%/ -7.18% +7.15%/ -6.23% +4.01%/ -9.10% +6.07%/-7.18% +9.58%/ -4.14% +8.28%/ -5.23% +7.81%/ -5.64% +6.00%/ -7.18% +7.27%/ -6.13% +7.81%/-5.64% +7.05%/ -6.31%
3.58MHz Crystal NTSC Square Pixel NTSC 601 NTSC 4fsc PAL Square Pixel PAL 601 PAL 4fsc 4.43MHz Crystal NTSC Square Pixel NTSC 601 NTSC 4fsc PAL Square Pixel PAL 601 PAL 4fsc
4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk= 4xClk=
49.09MHz 54.00MHz 57.27MHz 59.00MHz 54.00MHz 35.47MHz 49.09MHz 54.00MHz 57.27MHz 59.00MHz 54.00MHz 35.47MHz
+8.35%/ -5.19% +6.07%/ -7.18% +7.15%/ -6.23% +7.47%/ -5.93% +6.07%/-7.18% +7.64%/ -5.77% +8.28%/ -5.23% +7.81%/ -5.64% +6.00%/ -7.18% +7.27%/ -6.13% +7.81%/-5.64% +7.05%/ -6.31%
Table 4. NTSC/ PAL Clock Rate Range vs. Crystal Input DISABLING AUTOMATIC VCR SIGNAL DETECTION DEVICE ML6430 ML6431 DISABLE VCR SIGNAL DETECTION? No. Detection function is always on. Yes. Detection function can be disabled or enabled via serial bus only. This feature is enabled by default. Table 5. In the ML6430, the VCR detection circuit is always enabled. This circuit detects the presence of a VCR input signal at CVIN / HSYNC (pin 6) and automatically adjusts the gain settings for the digital PLL to optimize locking performance. This circuit scans for head switching greater than the thresholds selected by the user threshold bits (via serial bus) and then increases the phase gain of the digital PLL to compensate. In the ML6431, the VCR detection circuit operates the same as the ML6430 with the additional ability to disable or enable the VCR detection circuit to optimize for low jitter performance. This feature is enabled by default. This feature can be disabled in the ML6431 only by setting the appropriate values in Register 7, Bit 0 via the serial bus interface (see Table 11). When the VCR detect circuit is disabled, the ML6431 is optimized for low jitter performance. The 54MHz pin (pin 3) is an input that clocks the horizontal and vertical counters. In this mode, the ML6430 or ML6431 is used as a pulse generator. The input signal at can be any 4X clock; for example, 54MHz (4 x CCIR clock rate of 13.5MHz), 49.09MHz (4 x Square Pixel clock rate of 12.27MHz), or 57.27 MHz (4 x Fsc clock rate of 14.31MHz for NTSC color subcarrier). This input is limited to 70MHz. As a pulse generator, the sync, clamp, blanking, and clock signals are derived from the clock input at the 54MHz pin. This mode is activated by setting the appropriate values in Register 7 via the serial bus. See Tables 10 or 11. USING FRESET FOR NTSC vs. PAL MODES In NTSC mode, FRESET (pin 22) goes low on the high-tolow transition of the FIELD ID pin (pin 17) and the beginning of line 1 (see Figure 2). In the PAL mode, FRESET (pin 22)goes low on the low-tohigh transition of the FIELD ID pin and the end of line 310 (see Figure 3). PULSE GENERATOR MODE 54MHz Input or Any 4X Clock
10
ML6430/ML6431
FIELD 1 Vertical Blanking Interval
3H 525 1 2 3 4 3H 5 6 7 3H 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
H
Start of Field 1
H
H
H/2
H
FIELD 2 Vertical Blanking Interval
262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284
H/2
Start of Field 2 9 or 16 Lines
VBLANK Pin 24
FRESET Pin 22
1/2 Line
(Odd Vertical Intervals Only)
FIELDID Pin 17
Low For Odd Fields
FIELDID Pin 17
High For Even Fields
Figure 2. NTSC Field Rate Waveforms
FIELD BLANKING (25 LINES + LINE BLANKING) END OF FOURTH FIELD (ODD) WHITE LEVEL BEGINNING OF FIRST FIELD (EVEN)
BLACK LEVEL BLANKING LEVEL SYNC LEVEL
}
622
623
624
625
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
23
2.5 LINES 5 EQUALIZING PULSES END OF FIRST FIELD (EVEN) WHITE LEVEL
2.5 LINES FIELD SYNC 5 BROAD PULSES
2.5 LINES 5 EQUALIZING PULSES
BEGINNING OF SECOND FIELD (ODD)
BLACK LEVEL BLANKING LEVEL SYNC LEVEL
}
~
310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 336
VBLANK Pin 24 FRESET Pin 22 ODDFLD Pin 17
BROAD PULSE SEPARATION 4.7s 100ns 7.5 or 16 Lines
1/2 Line
(Second Field Vertical Interval Only)
High for Second Field, Low for First Field
Figure 3. PAL 625 Field Rate Waveforms
~
11
ML6430/ML6431
FUNCTIONAL DESCRIPTION
FREERUN MODE Both the ML6430 and ML6431 can be used in Freerun mode. The ML6431 is recommended for applications requiring a more robust Freerun mode of operations. Figure 4 and Figure 4a describe the state diagrams for both the ML6430 and ML6431. Note that the ML6431 includes a faster path to go from FREERUN MODE #1 to FREERUN MODE #2. Freerun mode: FREERUN MODE #1 is entered when the freerun pin is toggled high while the ML6430/ ML6431 is horizontally locked (i.e. internal horizontal locked signal is present). In this mode, the digital frequency value stored in the line-locked PLL is held and the ML6430/ML6431 will freerun at a frequency very close to that of the last locked video source. Freerun mode #1 is best used by physically tying the NoSignal pin to the freerun pin as shown in Figures 9 or 10. FREERUN MODE #2 is entered when the freerun pin is toggled high while the ML6430/Ml6431 (Continued) is not horizontally locked to a video source. In this mode, a ROM lookup table is used to set the freerun frequency of the ML6430/ML6431. In this mode the output frequency is as accurate as the Crystal plus the accuracy of the look up table. See Figures 4 and 4a for the NoSignal-Locked-Freerun state machine diagram. NoSignal: NoSignal will go low if video is present for one entire field. NoSignal will be high if video is not present for one entire field. Locked (ML6430): The ML6430 must be line (horizontal) locked to an input video source and also be vertically locked before the locked detect signal goes high. When a video source is removed, the locked signal may be high or low. Please note that the locked pin is the logical AND of the internal horizontal locked and vertical locked signals. For example, the internal horizontal locked signal may be high even though the locked pin is asserted low.
TOGGLE FREERUN PIN "HIGH" IF NO VIDEO FOR > 1 FRAME HORIZONTAL LOCKED POWER UP ML6430 W/ FREERUN PIN "LOW" (TYPICAL) SIGNAL PRESENT 2 HORIZONTAL LOCKED NO SIGNAL PRESENT IF INPUT VIDEO FOR > 1 FRAME 3 TOGGLE FREERUN PIN "HIGH" FREERUN PIN "LOW"
FREERUN MODE #1
5
INPUT VIDEO WITHIN 6% RANGE
INPUT VIDEO OUTSIDE 6% RANGE
IF NO VIDEO FOR > 1 FRAME HORIZONTAL UNLOCKED SIGNAL PRESENT 1 IF INPUT VIDEO FOR > 1 FRAME TOGGLE FREERUN PIN "HIGH" HORIZONTAL UNLOCKED NO SIGNAL PRESENT 4
FREERUN PIN "LOW" TOGGLE FREERUN PIN "HIGH" FREERUN MODE #2
6
POWER UP ML6430 W/ FREERUN PIN "HIGH" (TYPICAL)
Figure 4. ML6430 Freerun Mode State Diagram
12
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued) Table 6 first find the resolution and refresh rate required. Determine which crystal, PAL or NTSC is needed. Change the crystal to the proper frequency if necessary. Over the serial-bus, program the registers as indicated in Table 6. Supply to pin 6 an horizontal sync signal at TTL or CMOS levels and at the specified frequency. Trigger an oscilloscope on the falling edge of the horizontal input to view the outputs. The VGA pixel clock will be found on pin 18. Other useful signals are noted in table 6. External logic may be needed to produce usable vertical sync pulses. AUDIO CLOCKS VGA CLOCKS For VGA applications the ML6431 is recommended. Table 6 provides a list of the VGA clocks that can be generated using the ML6431. To use the information in The audio modes can be activated via serial bus (Register 7). When this mode is activated an audio clock frequency can be selected via serial bus (Register 8). See Table 9. Locked (ML6431): The ML6431 must be line (horizontal) locked to an input video source for at least two fields and also be vertically locked before the locked detect signal goes high. When a video source is removed, the ML6431 will lose horizontal lock after two entire fields with no video present. However, vertical lock may be lost before horizontal lock. Because the locked pin is the logical AND of the internal horizontal locked and vertical locked signals the locked pin may go low before the internal horizontal locked signal.
TOGGLE FREERUN PIN "HIGH" IF NO VIDEO FOR > 1 FRAME HORIZONTAL LOCKED POWER UP ML6431 W/ FREERUN PIN "LOW" (TYPICAL) SIGNAL PRESENT 2 HORIZONTAL LOCKED NO SIGNAL PRESENT IF INPUT VIDEO FOR > 1 FRAME 3 TOGGLE FREERUN PIN "HIGH" FREERUN PIN "LOW"
FREERUN MODE #1
5
INPUT VIDEO WITHIN 6% RANGE
INPUT VIDEO OUTSIDE 6% RANGE
IF NO VIDEO FOR > 2 FRAMES
IF NO VIDEO FOR > 1 FRAME HORIZONTAL UNLOCKED SIGNAL PRESENT 1 IF INPUT VIDEO FOR > 1 FRAME TOGGLE FREERUN PIN "HIGH" HORIZONTAL UNLOCKED NO SIGNAL PRESENT 4
FREERUN PIN "LOW" TOGGLE FREERUN PIN "HIGH" FREERUN MODE #2
6
POWER UP ML6431 W/ FREERUN PIN "HIGH" (TYPICAL)
Figure 4a. ML6431 Freerun Mode State Diagram
13
14
ML6431 Data Register Settings*
Resolution 640 x 480 # Pixels per Line 800 832 840 800 x 600 1024 1056 1040 1056 1024 x 768 1264 1344 1328 Refresh Rate 60 Hz 72 Hz 75 Hz 56 Hz 60 Hz 72 Hz 75 Hz 43 Hz/Int 60 Hz 70 Hz Horizontal Frequency 31.5 KHz 37.9 KHz 37.5 KHz 35.1 KHz 37.9 KHz 48.1 KHz 46.9 KHz 35.5 KHz 48.4 KHz 56.5 KHz Pixel Frequency 25.175 MHz 31.500 MHz 31.500 MHz 36.000 MHz 40.000 MHz 50.000 MHz 49.500 MHz 44.900 MHz 65.000 MHz 75.000 MHz Standard Type Industry VESA VESA VESA VESA VESA VESA Industry VESA VESA VG901101A VS910801-2 VS901101 VDMT75HZ VG900601 VG900602 VS900603A VDMT75HZ Original Standard # Freq. Std. NTSC Sq Pix =000 NTSC Sq Pix =000 NTSC Sq Pix =000 PAL 4FSC =101 PALXtal 1 0 0 1 1 1 1 0 0 0 Pixel Reg 572 640 656 512 544 528 544 752 832 816 PherrOut 0 0 0 1 1 1 1 1 1 1 VGA 1 1 1 1 1 1 1 1 1 1 External Xtal Used 4.43 4.43 4.43 4.43 3.58 4.43 4.43 4.43 4.43 3.58 Pixel Clk Output 2X 2X 2X 4X 4X 4X 4X 4X 4X 4X & clk doubler Horizontal Pulses Vertical Pulses "Hsync,Hreset" Vreset "Hsync,Hreset" Vreset "Hsync,Hreset" Vreset** "Hsync,Hreset" Vreset "Hsync,Hreset" Vreset** "Hsync,Hreset" Vreset** "Hsync,Hreset" Vreset** "Hsync,Hreset" Vreset** "Hsync,Hreset" Vreset** No No NTSC Sq Pix =000 NTSC Sq Pix =000 NTSC Sq Pix =000 PAL 4FSC =101 PAL 601 = 011 PAL 4FSC =101 *For Data Register Settings: TTL = High, VGA = On, VCR = Off, Noise Gating = On, Dis Auto Ver Det = 1 ** w/ external glue logic
ML6430/ML6431
Table 6. VGA Rates Supported
ML6430/ML6431
FUNCTIONAL DESCRIPTION
PRESET PIN CONTROL The ML6430/ML6431 may be controlled via a set of four preset mode pins. These pins do not allow access to all the programmable features of the ML6430/ML6431, but are intended to provide a simpler interface for most applications. (Continued) PULSE OUTPUTS Pulse outputs are defined in Table 12. Note that the pulse widths and start times are chosen to the nearest clock edge, and indicated errors assume nominal clock operating frequency.
P3 P2 P1 P0 0 1 1 0 1 1 0 1 1 0 1 1 0 Z Z 0 Z Z 1 0 1 1 0 1 1 0 1 1 0 1 Z 0 Z Z 0 Z 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 Z Z Z Z Z Z 1 1 1 1 1 1
STD NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC PAL PAL PAL
CLOCK RATE Square pixel CCIR601 4Fsc Square pixel CCIR601 4Fsc Square pixel CCIR601 4Fsc Square pixel CCIR601 4Fsc Square pixel CCIR601 4Fsc Square pixel CCIR601 4Fsc
CRYSTAL 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 4.43MHz 4.43MHz 4.43MHz 4.43MHz 4.43MHz 4.43MHz 14.32MHz 14.32MHz 14.32MHz 14.32MHz 14.32MHz 14.32MHz
P3 P2 P1 P0 0 Z Z 0 Z Z Z 1 0 Z 1 0 Z 1 0 Z 1 0 X Z 0 Z Z 0 Z 1 Z 0 1 Z 0 1 Z 0 1 Z 0 X 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 X Z Z Z Z Z Z 1 1 1 1 1 1 Z Z Z Z Z Z 0
STD NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC PAL PAL PAL NTSC NTSC NTSC PAL PAL PAL
CLOCK RATE Square pixel CCIR601 4Fsc Square pixel CCIR601 4Fsc Square pixel, VGA CCIR601,VGA 4Fsc, VGA Square pixel, VGA CCIR601, VGA 4Fsc, VGA Square pixel, VGA CCIR601, VGA 4Fsc, VGA Square pixel, VGA CCIR601, VGA 4Fsc, VGA Serial control mode
CRYSTAL 17.72MHz 17.72MHz 17.72MHz 17.72MHz 17.72MHz 17.72MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 3.58MHz 4.43MHz 4.43MHz 4.43MHz 4.43MHz 4.43MHz 4.43MHz
Z = Floating input, 0 = Low input, 1 = High input, X = Don't care
Table 7. Preset Pin Modes
15
ML6430/ML6431
FUNCTIONAL DESCRIPTION
CONTROL REGISTER INFORMATION REGISTER PulsePol[2:0] Clk4X Pixel[10:0] Burst CSyncRaw RawClamp TTL Sync WideBlank HDelay[6:0] Noise Gating Test 3,1,4 External 54 Clock IN FAud[1:0] VCR SLEEP Thresh[1:0] VGA Div4 Fstd[2:0] PALXTAL SETTING 000 0 Determined by PRESET pin 0 0 0 0 0 1000000 0 0, 0, 0 0 01 0 0 11 Determined by PRESET pin Determined by PRESET pin Determined by PRESET pin Determined by PRESET pin (Continued) RawClamp: Controls the source of the SCLAMP (sync clamp) pulse. Pulse is timed relative to incoming sync edge, or regenerated sync edge. PALXTAL: Controls the expected crystal frequency at the oscillator inputs. 0 = NTSC 3.58MHz, or 1 = PAL 4.43MHz. Thresh1,Thresh0: Selects the pixel error threshold at which relock is initiated. Values are: 0,0: 0,1: 1,0: 1,1: 2.5 pixels 2.5 pixels 1.0 pixels 4.0 pixels
Noise Gating: Enables a 3/4 line window to lockout any unwanted horizontal sync pulses. VGA: Produces non-interlaced progressive scan outputs. Div4: Controls the prescaler in the M/N loop. High means that 4Fs external oscillator signals are expected, low assumes a PAL or NTSC Fs crystal will be used. VCR: Controls the gain range and locking maneuvers of the digital loop. Provides better locking to the unpredictability of VCR headswitches and jitter. Blanking Width Control: The number of blanked lines in the vertical interval is programmable to either 9 or 16. XTAL: external Crystal Control: 0=NTSC 3.58MHz, or 1=PAL 4.43MHz, for both local crystal and external oscillator mode. External 54MHz Clock: This mode permits injecting a 54MHz clock (or other 4X clock) directly into the horizontal pixel counter via the SLEEP pin. All timing pulses are synchronous to the 54MHz clock (or other 4X clock). Serial Bus Control: To place the Ml6430/ML6431 in serial mode, take P0 (Preset ) to logical '0' or ground. The serial control system is written to by the external processor in 8bit bytes. Each of these bytes is partitioned into an address (upper 4 bits of serial byte) and a data register (lower 4 bits of serial byte). In Table 10, the Register heading refers to the 4-bit address, and Data Bit refers to a particular bit in the 4-bit register (Bit0 is LSB). Pixel: Program all bits to zero to enable default values for each standard. Otherwise use the following equation: P[10:0] = 2 (number of pixels per line) - 1024 Test: All test bits must be programmed to zero. (1)
Table 8. Default Control Register Settings for Preset Mode REGISTER DESCRIPTION SLEEP: Enables or disables sleep mode. When using serial bus control, ALL registers must be programmed to their intended state after power up to ensure correct operation of the ML6430/ML6431. CSR: Composite sync register bit controls whether composite sync output is from the sync separator, (raw CSYNC) or from the internal pulse generator (regenerated CSYNC). Pulse Polarity Control: The active state of output sync pulses, blanking pulses, or clamp pulses may be programmed to either 0 or 1 state by use of these bits. P0: CSYNC pulse output is high active when 1, low active when 0. P1: HBLANK, and VBLANK pulse outputs are high active when 1, low active when 0. P2: SCLAMP and BCLAMP pulse outputs are high active when 1, low active when 0. Burst: Controls the length of Burst Gate so pulse can be used for either burst gating in encoder applications or back porch clamping.
16
ML6430/ML6431
FUNCTIONAL DESCRIPTION
(Continued) This bit controls the source of AUDIOCLK/PHERROUT. When this bit is low, AUDIOCLK/PHERROUT provides the audio clock output. When this bit is high, AUDIOCLK/ PHERROUT provides the 1-bit digital phase error of each Hsync edge. Additionally, when both PHERROUT enable and VGA bits are logic high, the reset point of the pixel counter is changed from 512 to 256. This changes the equation for calculating the number of pixels per line verses the Pixel Counter bits to the following: P[10:0] = 2 (number of pixels per line) - 512 (2) Audio Clock: The Ml6430/ML6431 outputs a clock at 32kHz, 44.1kHz, or 48kHz. This clock is locked in frequency to the basic video clock regardless of the standard being used. With VCR head switches, the phase correction required to track the timing is removed from the audio clock by a patented circuit. This prevents the audio clock from being modulated by step changes in video timing. See the Table 9 for the audio clock rates supported and how they are derived internally. ADDITIONAL CONTROL REGISTERS (ML6431 ONLY) DisAutoVCR: Disables the auto VCR detect circuit. Register 7, Bit 0: DisAutoVCR PHERROUT: MUX phase error signal onto AUDIOCLK/PHERROUT pin. Register 7, Bit 3: PHERROUT enable
VIDEO STANDARD CCIR601 NTSC CCIR601 NTSC CCIR601 NTSC CCIR601 PAL CCIR601 PAL CCIR601 PAL NTSC Square Pixel NTSC Square Pixel NTSC Square Pixel PAL Square Pixel PAL Square Pixel PAL Square Pixel NTSC 4xFSC NTSC 4xFSC NTSC 4xFSC PAL 4xFSC PAL 4xFSC PAL 4xFSC
AUDIO RATE 48kHz 44.1kHz 32kHz 48kHz 44.1kHz 32kHz 48kHz 44.1kHz 32kHz 48kHz 44.1kHz 32kHz 48kHz 44.1kHz 32kHz 48kHz 44.1kHz 32kHz
AUDIO/PIXEL CLOCK RATIO (96000 / 27MHz) 13.5MHz (88200 / 27MHz) 13.5MHz (64000 / 27MHz) 13.5MHz (96000 / 27MHz) 13.5MHz (88200 / 27MHz) 13.5MHz (64000 / 27MHz) 13.5MHz (105600 / 27MHz) 12.27MHz (97020 / 27MHz) 12.27MHz (70400 / 27MHz) 12.27MHz (96000 / 29.5MHz) 14.75MHz (88200 / 29.5MHz) 14.75MHz (64000 / 29.5MHz) 14.75MHz (105600 / 31.5MHz) 14.32MHz (92400 / 30MHz) 14.32MHz (70400 / 31.5MHz) 14.32MHz (76800 / 28.37MHz) 17.72MHz (70560 / 28.37MHz) 17.72MHz (51200 / 28.37MHz) 17.72MHz
AUDIO/FRAME RATE RATIO (8008 / 5) 29.97Hz (147147 / 100) 29.97Hz (16016 / 15) 29.97Hz (1920) 25Hz (1764) 25Hz (1280) 25Hz (8008 / 5) 29.97Hz (147147 / 100) 29.97Hz (16016 / 15) 29.97Hz (1920) 25Hz (1764) 25Hz (1280) 25Hz (8008 / 5) 29.97Hz (147147 / 100) 29.97Hz (16016 / 15) 29.97Hz (1920) 25Hz (1764) 25Hz (1280) 25Hz
Table 9. Audio Clock Generation (ML6430/ML6431)
17
ML6430/ML6431
REGISTER 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6
DATA BIT 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 PulsePol 0 PulsePol 1 PulsePol 2 Clk 4X Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 Pixel7 Pixel8 Pixel9 Pixel10 Burst CSyncRaw RawClamp TTL Sync WideBlank HDelay0 HDelay1 HDelay2 HDelay3 HDelay4 HDelay5 HDelay6
DESCRIPTION CSYNC Polarity H/V Blank Polarity S/B Clamp Polarity Select 4X Clock Pix Counter Load Bit 0 Pix Counter Load Bit 1 Pix Counter Load Bit 2 Pix Counter Load Bit 3 Pix Counter Load Bit 4 Pix Counter Load Bit 5 Pix Counter Load Bit 6 Pix Counter Load Bit 7 Pix Counter Load Bit 8 Pix Counter Load Bit 9 Pix Counter Load Bit 10 Burst Gate Enable (or CSYNC Regen) (or Clamp Regen) TTL horizontal + vertical Sync Input (or Narrow)
VALUE RANGE High Active-Low Active High Active-Low Active High Active-Low Active Low 1X Clock = 13.5MHz High 4X Clock = 54MHz
BIT CODE RANGE 0 or 1 0 or 1 0 or 1 0 or 1
Numerical value taken as unsigned binary. Actual no. of pixels is: nom = ~011 0000 0000
512 +
P 10:0 2
max = 011 0011 0000 min = 010 1101 0000
Do not vary pixel [10:0] by more than 6% from nominal. 1024 > no. of pixels > 512 and fNOM x 1.06 > fNEW > fNOM x 0.94
Low = Back Porch Clamp High = Burst Gate Low = regenerated CSYNC High = raw CSYNC Low = regenerated Clamp High = raw Clamp Low = sync separator active High = TTL horiz + vert sync input Low = narrow blanking High = wide blanking
0 or 1 0 or 1 0 or 1 0 or 1 0 or 1
H Delay parameter allows moving the entire constellation of output pulses relative to the incoming HSYNC. Exception: Sync Tip clamp may be selected for delay or triggered from incoming sync depending on application.
0000000 to 1111111: 7-bit Horizontal Delay parameter. Values: -64p< Hdly < 63p, p = 1/F4XCLK 0000000 means -64p 1111111 means +63p 1000000 means 0p
Noise Gating 3/4 line lockout
Low = noise gating on High = noise gating off
0 or 1
Table 10. ML6430 Register Map
18
ML6430/ML6431
REGISTER 7 7 7 7 8 8 8 8 9 9 9 9 10 10 10 10
DATA BIT 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 Test 3 Test 1 Ext 54 Clock IN Test 4 FAud0 FAud1 VCR SLEEP Thresh0 Thresh1 VGA Div4 FStd0 FStd1 FStd2 PALXTAL
DESCRIPTION For test mode only: No user programmable features For test mode only: No user programmable features
VALUE RANGE
BIT CODE RANGE 0 0 0 or 1 0 00 to 10
Set to 0 Set to 0 Low = Pin 3 is SLEEP High = Pin 3 is 54MHz Clock
For test mode only: No user programmable features AudioClk Freq Bit 0 AudioClk Freq Bit 1 Enable VCR Mode Power Down Mode Select `Out of Lock' Threshold
Set to 0 00 = 48kHz, 01 = 44.1kHz, 10 = 32kHz
High = Enabled, Low = Disabled High = Power Down, Low = Normal 00 = 2.5 Pixels 01 = 2.5 Pixels 10 = 1.0 Pixels 11 = 4.0 Pixels 0 or 1 0 or 1 000 to 101 0 or 1 00 to 11
Enable VGA Mode Enable /4 on M/N Loop Freq Std Sel Bit 0 Freq Std Sel Bit 1 Freq Std Sel Bit 2 Enable PAL Ref Freq
High = Enabled, Low = Disabled High = Enabled, Low = Disabled 000 = NTSC Sq Pix 001 = PAL Sq Pix 010 = NTSC 601 011 = PAL 601 100 = NTSC 4Fsc 101 = PAL 4Fsc
High = Enabled, Low = Disabled
0 or 1
Table 10. ML6430 Register Map (Continued)
19
ML6430/ML6431
REGISTER 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6
DATA BIT 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 PulsePol 0 PulsePol 1 PulsePol 2 Clk 4X Pixel0 Pixel1 Pixel2 Pixel3 Pixel4 Pixel5 Pixel6 Pixel7 Pixel8 Pixel9 Pixel10 Burst CSyncRaw RawClamp TTL Sync WideBlank HDelay0 HDelay1 HDelay2 HDelay3 HDelay4 HDelay5 HDelay6
DESCRIPTION CSYNC Polarity H/V Blank Polarity S/B Clamp Polarity Select 4X Clock Pix Counter Load Bit 0 Pix Counter Load Bit 1 Pix Counter Load Bit 2 Pix Counter Load Bit 3 Pix Counter Load Bit 4 Pix Counter Load Bit 5 Pix Counter Load Bit 6 Pix Counter Load Bit 7 Pix Counter Load Bit 8 Pix Counter Load Bit 9 Pix Counter Load Bit 10 Burst Gate Enable (or CSYNC Regen) (or Clamp Regen) TTL horizontal + vertical Sync Input (or Narrow)
VALUE RANGE High Active-Low Active High Active-Low Active High Active-Low Active Low 1X Clock = 13.5MHz High 4X Clock = 54MHz Numerical value taken as unsigned binary. Actual no. of pixels is:
BIT CODE RANGE 0 or 1 0 or 1 0 or 1 0 or 1
512 +
P 10:0 2
nom = ~011 0000 0000
Do not vary pixel [10:0] by more than max = 011 0011 0000 6% from nominal. min = 010 1101 0000 1024 > no. of pixels > 512 and fNOM x 1.06 > fNEW > fNOM x 0.94 If PHERR enable and VGA = 1, the actual no. of pixels is: P[10:0]=2x(no. of pixels per line)-512 Low = Back Porch Clamp High = Burst Gate Low = regenerated CSYNC High = raw CSYNC Low = regenerated Clamp High = raw Clamp Low = sync separator active High = TTL horiz + vert sync input Low = narrow blanking High = wide blanking 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1
H Delay parameter allows moving the entire constellation of output pulses relative to the incoming HSYNC. Exception: Sync Tip clamp may be selected for delay or triggered from incoming sync depending on application.
0000000 to 1111111: 7-bit Horizontal Delay parameter. Values: -64p < Hdly < 63p, p = 1/F4XCLK 0000000 means -64p 1111111 means +63p 1000000 means 0p
Noise Gating 3/4 line lockout
Low = noise gating on High = noise gating off
0 or 1
Table 11. ML6431 Register Map
20
ML6430/ML6431
REGISTER 7 7 7 7
DATA BIT 0 1 2 3 DisAutoVCR Test 1 Ext 54 Clock IN
DESCRIPTION
VALUE RANGE 0=Auto VCR Detect ON 1=Disable Auto VCR Detect
BIT CODE RANGE 0 or 1
For test mode only: No user programmable features. Set to 0 Low = Pin 3 is SLEEP High = Pin 3 is Ext 54MHz Clock Low=Pin 16 is Audio CLK, Pin 3 is SLEEP High=Pin 16 is PHERROUT, Pin 3 is RESET 00 = 48kHz, 01 = 44.1kHz, 10 = 32kHz
0 0 or 1
PHERROUT or AUDIOCLK
0 or 1 00 to 10
8 8 8 8 9 9 9 9 10 10 10 10
0 1 2 3 0 1 2 3 0 1 2 3
FAud0 FAud1 VCR SLEEP Thresh0 Thresh1 VGA Div4 FStd0 FStd1 FStd2 PALXTAL
AudioClk Freq Bit 0 AudioClk Freq Bit 1 Enable VCR Mode Power Down Mode Select `Out of Lock' Threshold
High = Enabled, Low = Disabled High = Power Down, Low = Normal 00 = 2.5 Pixels 01 = 2.5 Pixels 10 = 1.0 Pixels 11 = 4.0 Pixels 0 or 1 0 or 1 000 to 100 00 to 11
Enable VGA Mode Enable /4 on M/N Loop Freq Std Sel Bit 0 Freq Std Sel Bit 1 Freq Std Sel Bit 2 Enable PAL Ref Freq
High = Enabled, Low = Disabled High = Enabled, Low = Disabled 000 = NTSC SqPix 001 = PAL Sq Pix 010 = NTSC 601 High = Enabled, Low = Disabled 011 = PAL 601 100 = NTSC 4Fsc
0 or 1
Table 11. ML6431 Register Map (Continued)
21
ML6430/ML6431
FUNCTIONAL DESCRIPTION
SERIAL BUS OPERATION The serial bus control in the ML6430/ML6431 has two levels of addressing: Device Addressing and Register Addressing. Device Addressing: Figure 5 shows the physical waveforms generated in order to address the ML6430/ ML6431. There are six basic parts of the waveform: 1. Start Indication: Clock Cycle 0 2. Device Address Shifted: Clock Cycle 1 through 8 3. Device Address Strobed and Decoded: Clock Cycle 9 (Continued) 4. Data Shifted : Clock Cycle 10 through 17 5. Data Strobed into Appropriate Register: Clock Cycle 18 6. Stop indication: Clock Cycle 19 Register Addressing: Figure 6 shows the register map of the ML6430/6431. There are two basic parts of each received data byte: Address Nibble and Data Nibble 1. Address Nibble: The upper 4 bits of the data byte gives the register number in which to place the data. 2. Data Nibble: The lower 4 bits of the data byte is the data to be placed in the currently addressed register nibble.
START SDATA tRISE All Other SDATA Transitions Must Occur While SCLK is Low tSET/START SCLK START: A Falling Edge on the SDATA While SCLK is Held High STOP: A Rising Edge on the SDATA While SCLK is Held High STOP tFALL
Figure 5. Definition of START & STOP on Serial Data Bus
SDATA
MSB A7 A6 A1 A0
MSB D7 D6 D1 D0 STOP
SCLK 0 1 2 7 8 9 10 11 16 17 18
SCLK: SCLK: SCLK: SCLK: SCLK:
9th pulse strobes address decoder Rising edge enables data transfer Falling edge disables data transfer Rising edge enables data transfer Falling edge in prep for first address transfer
SDATA: Rising edge with SCLK Hi = STOP SDATA: Value set low in prep for STOP SCLK: SCLK: SCLK: SCLK: 18th pulse strobes data shift register Rising edge enables data transfer Falling edge disables data transfer Rising edge enables data transfer
SDATA: Value set to A6, Device Address (MSB-1)
SDATA: Value set to D6, Data MSB-1
SDATA: Value set to A7, Device Address MSB SDATA; Falling edge with SCLK Hi means start of sequence
SDATA: Value set to D7, Data MSB
Figure 6. Definition of DATA FORMAT on Serial Data Bus
22
ML6430/ML6431
SDATA `1' `0' `1' `1' `0' `0' `1' `0' O R3 R2 R1 R0 D3 D2 D1 D0
STROBE O
DEVICE ADDR = `B2' SCLK 0 1 2 3 4 5 6 7 8 9 A
REGISTER SUB-ADDR B C D E F
DATA
G
H
I
SCLK:
Address decode strobed on 9th clock [Data is `don't care' during strobe] SDATA: Final Clock strobes data into register SDATA: Second 4 bits are Register Data SDATA: First 4 bits are Register Address
SDATA: `1011 0010' shifted on next 8 clocks SCLK: Falling edge in prep for device address transfer
Figure 7. Typical Serial Bus Command
SDATA
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
0
SCLK
START
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
I
STOP
Register Address
Data Data Strobed into
Device Address
Strobe in Address
Appropriate Register
Figure 8. Serial Bus Command to Set Bit #2 in Register 7
23
ML6430/ML6431
APPLICATIONS
The ML6430 and ML6431 can be used for a variety of applications. The following figures provide a basic setup for the various applications listed below: Figure 9: ML6430 or ML6431 in NTSC CCIR Applications Figure 10: ML6430 or ML6431 in PAL CCIR Applications Figure 11: ML6431 in VGA Application Figure 12: ML6430 or ML6431 in Audio Applications Figure 13: ML6430 or ML6431 in Pulse Generator Applications
24
ML6430/ML6431
5V
5V for 3.54 MHz XTAL or open for 4.43 MHz XTAL
1.0F CVSYNCH OUT 0.1F
BCLAMP/BURST
32 P2/SDATA 5V P3/SCLK SLEEP/54MHz 5V 0.1F 0.001F VCC S GND S CVIN/HSYNC 1.0F CV in 1.0F CVREF VSYNC 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 VBLANK HRESET FRESET VCC B GND B 1X CLOCK/4X CLOCK 2X CLOCK FIELD ID 5V 0.1F 1nF
ML6430/ML6431
10
11
12
13
14
15
17 16
XTALIN
XTALOUT
NOSIGNAL
75
3.58MHz or 4.43MHz 400 1nF 0.1F 5V LED 5V
410
5V LED
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A) *PHERROUT is only available with the ML6431
Figure 9. ML6430/ML6431 in NTSC CCIR Applications Programmed via Preset Pins
AUDIOCLK/PHERROUT*
FREERUN
LOCKED
GND A
VCC A
HBLANK
21 20 19 18
GND D
VCC D
SCLAMP
CSYNC
P1
P0
25
ML6430/ML6431
5V
5V for 3.54 MHz XTAL or open for 4.43 MHz XTAL 5V
1.0F CVSYNCH OUT 0.1F
BCLAMP/BURST
32 P2/SDATA 5V P3/SCLK SLEEP/54MHz +5V 0.1F 0.001F VCC S GND S CVIN/HSYNC 1.0F CV in 1.0F CVREF VSYNC 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 VBLANK HRESET FRESET VCC B GND B 1X CLOCK/4X CLOCK 2X CLOCK FIELD ID 5V 0.1F 1nF
ML6431
10
11
12
13
14
15
17 16
XTALIN
XTALOUT
NOSIGNAL
75
3.58MHz 400 or 4.43MHz 1nF 0.1F 5V LED 5V
410
5V LED
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A) *PHERROUT is only available with the ML6431
Figure 10. ML6430/ML6431 in PAL CCIR Applications Programmed via Preset Pins
26
AUDIOCLK/PHERROUT*
FREERUN
LOCKED
GND A
VCC A
HBLANK
21 20 19 18
GND D
VCC D
SCLAMP
CSYNC
P1
P0
ML6430/ML6431
5V
1.0F CVSYNCH OUT 0.1F
BCLAMP/BURST
32 SDATA SCLK P2/SDATA P3/SCLK SLEEP/54MHz 5V 0.1F 0.001F VCC S GND S CVIN/HSYNC HSYNC OR CV 1.0F CVREF VSYNC 1 2 3 4 5 6 7 8 9
VCC A
31
30
29
28
27
26
25 24 23 22 VBLANK HRESET FRESET VCC B GND B 1X CLOCK/4X CLOCK 2X CLOCK FIELD ID PIXEL CLOCK OUTPUT 5V 0.1F 1nF
ML6431
10
GND A
11
XTALIN
12
XTALOUT
13
FREERUN
14
NOSIGNAL
15
LOCKED
17 16
AUDIOCLK/PHERROUT*
3.58MHz or 4.43MHz 400 1nF 0.1F 5V LED 5V
410
5V LED
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A) *PHERROUT is only available with the ML6431
Figure 11. ML6431 in VGA Applications
HBLANK
GND D
VCC D
SCLAMP
CSYNC
P1
P0
21 20 19 18
27
ML6430/ML6431
5V
1.0F CVSYNCH OUT 0.1F
BCLAMP/BURST
32 SDATA SCLK P2/SDATA P3/SCLK SLEEP/54MHz 5V 0.1F 0.001F VCC S GND S CVIN/HSYNC 1.0F 1.0F CV in 75 CVREF VSYNC 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 VBLANK HRESET FRESET VCC B GND B 1X CLOCK/4X CLOCK 2X CLOCK FIELD ID 5V 0.1F 1nF
ML6430/ML6431
10
11
12
13
14
15
17 16
XTALIN
XTALOUT
GND A
NOSIGNAL
FREERUN
LOCKED
3.58MHz or 4.43 MHz 400 1nF 0.1F 5V LED 5V
AUDIOCLK/PHERROUT*
VCC A
HBLANK
21 20 19 18
GND D
VCC D
SCLAMP
CSYNC
P1
P0
AUDIO CLOCK OUT
410
5V LED
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A) Note 2. See Table 4 for audio clock frequencies and registers *PHERROUT is only available with the ML6431
Figure 12. ML6430/ML6431 in Audio Applications
28
ML6430/ML6431
5V
1.0F CVSYNCH OUT 0.1F See Table 7 for Available Standards
BCLAMP/BURST
32 P2/SDATA P3/SCLK SLEEP/54MHz 5V 0.1F 0.001F VCC S GND S CVIN/HSYNC 1.0F 1.0F NO INPUT NEEDED CV in 75 CVREF VSYNC 1 2 3 4 5 6 7 8 9
31
30
29
28
27
26
25 24 23 22 VBLANK HRESET FRESET VCC B GND B 1X CLOCK/4X CLOCK 2X CLOCK FIELD ID 5V 0.1F 1nF
ML6430/ML6431
10
11
12
13
14
15
17 16
XTALIN
XTALOUT
GND A
NOSIGNAL
FREERUN
LOCKED
3.58MHz or 4.43 MHz 400 1nF 0.1F 5V LED 5V
AUDIOCLK/PHERROUT*
VCC A
HBLANK
21 20 19 18
GND D
VCC D
SCLAMP
CSYNC
P1
P0
AUDIO CLOCK OUT
410
5V LED
Note 1. For minimum VCC bypassing, connect capacitors VCCA only. (VCCA to GND A) Note 2. See Table 4 for audio clock frequencies and registers *PHERROUT is only available with the ML6431
Figure 13. ML6430/ML6431 in Pulse Generator Applications
29
ML6430/ML6431
NTSC AT SQUARE PIXEL RATE
SYMBOL N HA NH NVA NV NAME: DESCRIPTION Clocks per H: Active Clocks per H: Whole Line H per Frame: Active H per Frame: Whole Line CCIR 601STD 640 780 486 525 16 9 63.55 0.0 4.7 TYP 648 780 493,507 525 15 9 63.55 0.0 4.73 41 2.35 2.28 27.05 300 1.5 300 2.51 4.0 -1.5 10.9 122 1.47 326 2.44 3.91 -1.39 10.76 UNITS cycles cycles lines lines lines lines s s s s s s ns s ns s s s s
PAL AT SQUARE PIXEL RATE
SYMBOL N HA NH NVA NV NAME: DESCRIPTION Clocks per H: Active Clocks per H: Whole Line H per Frame: Active H per Frame: Whole Line 625 CCIR 601STD 768 944 TYP 767 944 609, 616 625 15 9 64.0 0.0 4.7 64.0 0.0 4.68 34 2.35 27.3 300 1.5 300 2.43 4.0 -1.5 12.0 2.31 27.32 102 1.49 339 2.44 4.0 -1.49 12.0 UNITS cycles cycles lines lines lines lines s s s s s s ns s ns s s s s
NVBLKW Lines of Blanking: Wide NVBLKN tH tHS tHSW tHRW tHEQW Lines of Blanking: Narrow H Line Time H Sync Time H Sync Width H Reset Width Equalizer Sync Width
NVBLKW Lines of Blanking: Wide NVBLKN Lines of Blanking: Narrow tH tHS tHSW tHRW tHEQW H Line Time H Sync Time H Sync Width H Reset Width Equalizer Sync Width
tHSERRW Serration Sync Width tHSTC tHSTCW tHBPC tHBPGW tHBPCW tHBLK tHBLKW Sync Tip Clamp Pulse Sync Tip Clamp Width BurstPulse BurstWidth B Clamp Width H Blanking Pulse H Blanking Pulse Width
tHSERRW Serration Sync Width t HSTC t HSTCW t HBPC Sync Tip Clamp Pulse Sync Tip Clamp Width BurstPulse
t HBPGW BurstWidth t HBPCW B Clamp Width tHBLK tHBLKW H Blanking Pulse H Blanking Pulse Width
Table 12. Pulse Output Timing
30
ML6430/ML6431
NTSC AT 4 X FS RATE
SYMBOL N HA NH NVA NV NAME: DESCRIPTION Clocks per H: Active Clocks per H: Whole Line H per Frame: Active H per Frame: Whole Line CCIR 601STD 768 910 486 525 16 9 63.55 0.0 4.7 TYP 752 910 493,507 525 15 9 63.55 0.0 4.68 35 2.35 27.05 300 1.5 300 2.51 4.0 -1.5 10.9 2.30 27.02 105 1.47 349 2.51 3.98 -1.54 11.03 UNITS cycles cycles lines lines lines lines s s s s s s ns s ns s s s s
PAL AT 4 X FS RATE
SYMBOL N HA NH NVA NV NAME: DESCRIPTION Clocks per H: Active Clocks per H: Whole Line H per Frame: Active H per Frame: Whole Line 625 CCIR 601STD 922 1135.0064 TYP 922 1135 609, 616 625 15 9 64.0 0.0 4.7 64.0 0.0 4.74 28 2.35 27.3 300 1.5 300 2.43 4.0 -1.5 12.0 2.25 27.29 169 1.58 225 2.48 4.06 -1.52 12.12 UNITS cycles cycles lines lines lines lines s s s s s s ns s ns s s s s
NVBLKW Lines of Blanking: Wide NVBLKN tH tHS tHSW tHRW tHEQW tHSERRW tHSTC tHSTCW tHBPC tHBPGW tHBPCW tHBLK tHBLKW Lines of Blanking: Narrow H Line Time H Sync Time H Sync Width H Reset Width Equalizer Sync Width Serration Sync Width Sync Tip Clamp Pulse Sync Tip Clamp Width BurstPulse BurstWidth B Clamp Width H Blanking Pulse H Blanking Pulse Width
NVBLKW Lines of Blanking: Wide NVBLKN tH tHS tHSW tHRW tHEQW Lines of Blanking: Narrow H Line Time H Sync Time H Sync Width H Reset Width Equalizer Sync Width
tHSERRW Serration Sync Width tHSTC tHSTCW tHBPC tHBPGW tHBPCW tHBLK tHBLKW Sync Tip Clamp Pulse Sync Tip Clamp Width BurstPulse BurstWidth B Clamp Width H Blanking Pulse H Blanking Pulse Width
Table 12. Pulse Output Timing (Continued)
31
ML6430/ML6431
NTSC AT CCIR601 RATE
SYMBOL N HA NH NVA NV NAME: DESCRIPTION Clocks per H: Active Clocks per H: Whole Line H per Frame: Active H per Frame: Whole Line CCIR 601STD 720 858 486 525 16 9 63.55 0.0 4.7 TYP 709 858 493, 507 525 15 9 63.55 0.0 4.67 37 2.35 27.05 300 1.5 300 2.51 4.0 -1.5 10.9 2.37 27.04 111 1.48 370 2.44 4.10 -1.55 11.03 UNITS cycles cycles lines lines lines lines s s s s s s ns s ns s s s s
PAL AT CCIR601 RATE
SYMBOL N HA NH NVA NV NAME: DESCRIPTION Clocks per H: Active Clocks per H: Whole Line H per Frame: Active H per Frame: Whole Line 625 CCIR 601STD 720 864 TYP 702 864 609, 616 625 15 9 64.0 0.0 4.7 64.0 0.0 4.67 37 2.35 27.30 300 1.5 300 2.43 4.0 -1.5 12.0 2.30 27.33 111 1.48 370 2.44 4.0 -1.48 12.0 UNITS cycles cycles lines lines lines lines s s s s s s ns s ns s s s s
NVBLKW Lines of Blanking: Wide NVBLKN Lines of Blanking: Narrow tH tHS tHSW tHRW tHEQW H Line Time H Sync Time H Sync Width H Reset Width Equalizer Sync Width
NVBLKW Lines of Blanking: Wide NVBLKN tH tHS tHSW tHRW tHEQW Lines of Blanking: Narrow H Line Time H Sync Time H Sync Width H Reset Width Equalizer Sync Width
tHSERRW Serration Sync Width t HSTC t HSTCW t HBPC Sync Tip Clamp Pulse Sync Tip Clamp Width BurstPulse
tHSERRW Serration Sync Width tHSTC tHSTCW tHBPC tHBPGW tHBPCW tHBLK tHBLKW Sync Tip Clamp Pulse Sync Tip Clamp Width BurstPulse BurstWidth B Clamp Width H Blanking Pulse H Blanking Pulse Width
tHBPGW BurstWidth t HBPCW B Clamp Width tHBLK tHBLKW H Blanking Pulse H Blanking Pulse Width
Table 12. Pulse Output Timing (Continued)
32
ML6430/ML6431
PHYSICAL DIMENSIONS
inches (millimeters)
Package: H32-7 32-Pin (7 x 7 x 1mm) TQFP
0.354 BSC (9.00 BSC) 0.276 BSC (7.00 BSC) 25 0 - 8 0.003 - 0.008 (0.09 - 0.20)
1 PIN 1 ID 0.276 BSC (7.00 BSC) 0.354 BSC (9.00 BSC)
17
0.018 - 0.030 (0.45 - 0.75)
9 0.032 BSC (0.8 BSC) 0.012 - 0.018 (0.29 - 0.45) 0.048 MAX (1.20 MAX) 0.037 - 0.041 (0.95 - 1.05) SEATING PLANE
ORDERING INFORMATION
PART NUMBER ML6430CH ML6431CH (EOL) TEMPERATURE RANGE 0C to 70C 0C to 70C PACKAGE 32-Pin TQFP (H32-7) 32-Pin TQFP (H32-7)
(c) Micro Linear 2000. property of their respective owners.
is a registered trademark of Micro Linear Corporation. All other trademarks are the
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document. The circuits contained in this document are offered as possible applications only. Particular uses or applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications. 2092 Concourse Drive San Jose, CA 95131 Tel: 408/433-5200 Fax: 408/432-0295 www.microlinear.com
DS6430_31-01
33

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